The advantage of high rate clock in the DVB system results in a higher decode speed in the Modified Euclidean algorithm block,optimization of the pipeline structure of the decoder and efficient reduction of the chip area.

Some optimization techniques such as 4-level pipeline structure and ROM data compression are used in the design.

Considering both the speed and the complexity,this method uses three-stage pipeline structures based on Radix-4 algorithm by DIT.

To further increase the throughput the three stage pipeline architecture is adopted inside the processing element, so that every one bit result outputs at one clock cycle when the pipeline is filled.

In this paper,an optimized single-symbol 3-stage pipeline architecture for AE is presented,which makes up the flaws of the existing ones.

Compared with the full parallel architecture,the memory cost of the designed processor decreases,thus the speed is higher than that of the SDF pipeline architecture.

Through pipeline, the latency of decoding process reduces dramatically.

This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter(ADC)based on an improved 1.

A high-speed low-power pipeline A/D converter is designed in this paper.

Radix-4 pipelined architecture is adopted for 16 and 64 points computation.

Without any other additional circuit, the algorithm achieved a pipelined architecture of rounding method by adjusting the quantization level, the quantization error ranged from -1/2LSB to 1/2LSB.

This paper adopted the technology of pipelined architecture A/D conversion and designed a A/D convertor of 10 bits resolution factor、10 MSPS sampling speed with nine-stage pipelined architecture of 1.

The algorithm is calculated on a parallel pipeline architecture hardware platform which consists of two TMS320C25 chip.