If the RCS-900 protection adopts the 2048kbit/s multiplex channel, slips may occur in the receiving code of the protective equipment while the retiming function of the channel is on and the communication clock of the protective equipment is set in the inner clock mode.

A new clock-feedthrough reduction technology for switched current circuits;

A new clock-feedthrough(CFT) compensation technology for switched-current circuits is described.

This paper analysis the theory of the comparator and the method of how to decrease the channel charge injection and clock feedthrough,the method can effectively improved the performance of switch capacitor.

Compared with the synchronized counter,the asynchronous counter faced two prominent difficult questions in design: One is the selection of clock signals of various triggers,the other is the correct gain of the karnaugh map at the time when the is simplified into the equation of state for varions triggers.

On the base of the traditional approaches for designing synchronous sequential circuits,a new approach for designing asynchronous sequential logic circuit is proposed in this paper where the trigger pulses can be directly obtained from sequential waveforms in sequential circuits,and the next state Karnaugh maps can be acomplished according to the state transformations caused by clock signals.

This paper introduces IBIS model and its applications in the design of computer high-speed system, and gives the waveform of clock signal simulation in detail.