1) ECL double-edge-triggered D flip-flop
ECL双边沿D触发器
1.
The ECL OR-AND-gate can simplify a generalized ECL circuits structures,for example,an ECL double-edge-triggered D flip-flop.
8V,作为常规ECL门的补充类型,常可用于简化一般ECL电路结构,例如ECL双边沿D触发器。
2) double-edge-triggered D flip-flop
双边沿D触发器
1.
Design of multi-valued double-edge-triggered D flip-flop based on clock-controlled neuron MOS transistor
基于钟控神经MOS管的多值双边沿D触发器设计
4) double-edge-triggered flip-flop
双边沿触发器
1.
Design of low power multivalued double-edge-triggered flip-flop;
多值低功耗双边沿触发器设计
2.
The application of this type of double-edge-triggered flip-flop in seq.
从双边沿触发器的特点出发,提出了一种双边沿动态触发器的设计方案,该触发器结构较其他几种设计方案简单。
5) Double edge trigger
双边沿触发
1.
Design of low power Flip-Flop based on double edge trigger;
基于双边沿触发的低功耗触发器逻辑设计
6) double edge triggered counter
双边沿触发计数器
1.
Design of low power all digital phase-locked loop based on double edge triggered counter;
基于双边沿触发计数器的低功耗全数字锁相环的设计
2.
A double edge triggered counter is designed, and the redundancy attribute of the circuit is utilized to decrease the power consumption of the system.
设计了双边沿触发计数器,并利用电路的冗余特性,降低了系统的功耗。
补充资料：边沿
边缘①：～地带。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条