Design of An Improved ADPLL Base on FPGA;

The design of self-sampling PI control all digital phase-locked loop(ADPLL) is implemented on the FPGA chip.

A mathematical model is developed to derive the related parameters of the ADPLL.

A fast all digital phase-locked loop with automatic modulus control is presented.

With the flying development of large scale and super high speed integrated circuit, the integration of digital system becomes higher and higher, and the logic speed becomes faster and faster, which makes the application of all digital phase-locked loop in every domain of digital communication, control project and wireless electronics more and more extensive.

In this paper,a method that realizes all digital phase-locked loop by Verilog hardware description language is presented.

The Design and Realization of a Kind of DPLL Using a N before M Loop Filter;

DCO is a key module of DPLL,generally there are two design methods:N devided counter control and increment/decrement counter control.

After analyzing the common technologies of the commercial digital phase locked loop (DPLL) and the features of the low frequency signals, this paper proposed an implement method of PLL based on CPLD which is applicable to low frequency signals.

So it is very important to design an all-digital phase-locked loop which is with high performance and compatible with digital circuits.

This paper proposes a new z-domain model for all-digital phase-locked loop(ADPLL)whose output frequency is inversely proportional to the control word of digital controlled oscillator(DCO).

A design method for all DPLLs that with low power cost and high phase locked velocity has been proposed.

Through VHDL hardware description language and increasing state detection of function module in PLL,the detection of working state of PLL(out of lock or lockage)can be realized in the chip of all-digitized phase lock loop realized by FPGA programmable technology.