1) co-verification
协同验证
1.
Design of Co-verification Environment Using SystemC Kernel with Native ISS;
集成ISS的SystemC内核的协同验证环境设计
2.
A Hardware-Software Co-verification Method for SOC Design;
片上系统设计中软硬件协同验证方法的研究
3.
This paper presents a novel SoC co-verification environment based on the C simulation strategy.
基于C仿真策略建立了一种新的SoC软/硬件协同验证环境。
2) Software/hardware co-verification
软硬件协同验证
1.
With respect to the verification bottleneck of current digital ASICs design and for the purpose of describing and verifying design object in a higher abstract level,a software/hardware co-verification method is presented,the method is based on processor core model of SystemC and others model of Verilog.
针对当前专用数字集成电路设计中的验证瓶颈,为了在更高的抽象级别对设计时象进行描述和验证,提出一种软硬件协同验证方法。
2.
A number of vertex processing unit programs on the platform had been run using software/hardware co-verification methods.
在该平台上,采用软硬件协同验证的方法,成功地运行了多个顶点处理器程序。
3) mixed level co-verification
混合级协同验证
4) hardware/software co-verification
软/硬件协同验证
1.
Implementation of efficient debug in virtual prototyping based on hardware/software co-verification;
基于虚拟原型机的软/硬件协同验证中高效调试手段的实现
6) Co-synthesis and verification
协同综合与验证
补充资料：DVT 设计验证(Design Verification Testing)
以测试产品的功能性为主，通常还包含Debug。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条