1) time scheduling Verification platform
时序验证平台
2) testbench
验证平台
1.
Research and Application of an Efficient Testbench Based on Verilog;
基于VERILOG的一种高效验证平台的研究及应用
2.
Since systemC language was good at behavior description,design method of behavior models and testbenchs using systemC instead of HDL in IP soft core design were introduced in this paper.
在IP软核的设计过程中,可以利用SystemC行为模型描述特点代替传统HDL语言,建立行为模型和验证平台。
3.
Based on these research,a relevant testbench design is proposed.
分析了IP核设计过程中功能验证的重要性,研究了CIU96B IP核设计,在此基础上提出了一个相应的验证平台设计,仿真显示该验证平台结构的实现了对该IP核的验证,有效地促进了该IP核的设计。
3) verification platform
验证平台
1.
Construction of verification platform based on SD/MMC controller;
基于RVM SD/MMC卡控制器验证平台的搭建
2.
Design and Application of Microprocessor Hardware Verification Platform;
微处理器硬件验证平台的设计与应用
3.
Design of FPGA verification platform of 32 bits RISC microprocessor;
32位RISC微处理器FPGA验证平台设计与实现
4) timing verification
时序验证
1.
An approach how to check the setup time and the hold time of the integrated circuit port signal with the aid of the timing check system in the integrated circuit timing verification stage is introduced in this article.
论文介绍了在集成电路时序验证阶段如何借助时序检测系统对集成电路端口信号的建立时间和保持时间进行检测。
2.
A timing verification research on the general processor used for communication and network is written in this dissertation.
论文对一个用于通信和网络的通用通信处理器的时序验证进行了研究。
5) RVM TestBench
RVM验证平台
6) fpga verification platform
FPGA验证平台
1.
This paper als o introduces the FPGA verification platform in detail since verification is of c ritical importance for the success of a.
264解码器的ASIC(专用芯片)解决方案及其FPGA验证平台。
补充资料：时序女神
时序女神(horae)：宙斯和忒弥斯诸女，
欧诺弥亚(eunomia）秩序女神
狄刻(dike)公正女神
厄瑞涅(eirene）和平女神.
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条