On the base of the traditional approaches for designing synchronous sequential circuits,a new approach for designing asynchronous sequential logic circuit is proposed in this paper where the trigger pulses can be directly obtained from sequential waveforms in sequential circuits,and the next state Karnaugh maps can be acomplished according to the state transformations caused by clock signals.

The realization method of three inner function modules of FPGA based on quartus Ⅱplatform is expatiated and the timing simulation waveform of these modules is given.

This paper focuses on the PCI bus I/O measurement techniques and analysis methods to write timing waveform,measured Hua Xia Imperial family Main Board PCI waveform write cycle time,and the simulation result shows that the method is feasible and effective.

Equivalent time-frequency method(ETFM) is used to extract features for PD pulse shape-time sequence detected by UWB with a sampling rate of 108 per second.