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1)  floating point calculator
浮点运算器
1.
Design and implementation of floating point calculator based on FPGA technology;
基于FPGA技术的浮点运算器的设计与实现
2.
At the same time, application examples of a floating point calculator and a micro controller are given.
介绍了基于 FPGA技术的计算机组成原理实验系统的组成和特点 ,同时给出了在该实验系统上实现的浮点运算器和微控制器实例。
2)  floating-point arithmetic
浮点运算
1.
This paper analyzes the causes of error resulted from many ways, such as floating-point arithmetic, temperature, pressure measuring loop, choice of sampling cycle, so that the problems can be noticed.
流量积算(或显示)仪是一种多参量综合计算的仪表,最终结果的准确度是各环节的综合误差,本文就多次浮点运算、温度、压力测量回路、采样周期的选取等方面分析产生误差的原因,以便在设计时引起注意。
2.
To improve the floating-point arithmetic performance of Navigation Computer,and to meet the requirement of real-time performance of integrated navigation system,a navigation computer with floating-point auxiliary processor is proposed.
为了提高导航计算机的浮点运算性能,满足组合导航系统实时性的要求,在基于FPGA的嵌入式导航计算机中,利用新型FPGA的片内逻辑资源,设计出专门用于浮点运算的协处理器单元,实现了组合导航浮点运算的硬件执行。
3.
The hardware implementation is very difficult because of floating-point arithmetic disadvantage of complex computation and too much hardware resource consuming.
浮点运算因其运算步骤繁琐及硬件资源消耗大等缺点使得浮点LMS算法的硬件实现十分困难。
3)  floating operation
浮点运算
1.
Step motor is a kind of flexible control equipment, on the other hand, DSP has high speed and floating operation capacity.
步进电机是非常灵活的控制元件 ,TMS32 0C31DSP是快速的、支持浮点运算的微处理器 ,将两者优点结合起来 ,就能在某些控制中得心应手。
4)  floating point operation
浮点运算
1.
The design has been used in the IP software core design of 32 b complex floating point operation as a module,and acquire a g.
总结浮点运算中前导0/1问题的解决办法,阐述各种方法的原理和实现方法,用VHDL硬件描述语言描述,并进行仿真和综合。
5)  float number operation
浮点运算
1.
Implementation of float number operation on CPLD/FPGA chip by VHDL;
用VHDL语言在CPLD/FPGA上实现浮点运算
6)  floating-point operation
浮点运算
1.
In view of some characteristics of digital image,a new method of floating-point operation is implemented on a ordinary FPGA chip.
针对数字图像本身存在的特点,提出了一种基于FPGA的浮点运算方法。
2.
According to floating-point operation process, the floating-point operations are divided into three stages, namely, the pre-normalization stage, calculation stage and post-normalization stage.
目前,随着信息应用领域对数据运算精度要求的不断提高和数值运算范围的不断扩大,使得在当今CPU的设计中,浮点运算单元的研究显得越来越重要。
3.
The fixed-point multiplier-adder is used to implement floating-point operation,which is simulated and implemented on FPGA.
利用定点乘加器完成浮点运算,并在FPGA中进行了仿真及实现。
补充资料:浮点运算
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性质:把一个数表示为尾数部分和指数部分,则称该数为浮点数(floating point number)。例如十进制数为+63.8写成浮点数则为0.638×102,其中+0.638是尾数部分,102是指数部分。对浮点数进行的算术运算称为浮点运算。

说明:补充资料仅用于学习参考,请勿用于其它任何用途。
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