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1)  path delay test
通路时延测试
2)  delay test
时延测试
1.
An instruction-based path delay test generation method for the datapath of a processor is proposed,which apply the processor s own instructions in normal operation mode to test itself.
针对处理器的数据通路中的通路时延故障,提出一种基于指令集的处理器时延测试产生方法。
2.
As the speed of microprocessors approaches the gigahertz range, delay test is becoming increasingly critical in industry and receives more attention in research field.
这使得处理器的测试面临着越来越多的挑战,特别是处理器的时延测试已成为工程应用的需要和测试研究领域的热点。
3)  delay testing
时延测试
1.
Test Generation Based on Behavioral Model at RT-level and Delay Testing;
基于RTL行为模型的测试产生及时延测试方法
2.
At the same time, it is also more critical to perform delay testing to ensure correct temporal behavior of fast digital systems than before.
寄存器传输级(RTL)测试产生及时延测试是当今集成电路(IC)测试技术中亟待解决的问题和研究的热点。
3.
This paper gives a survey of the recent development of path delay testing,introduces the classification of single path delay faults according to testability,and analyses three approaches to reducing the number of paths to be tested during path delay testin
本文对目前通路时延测试领域的主要研究成果进行了综述 ,阐述了主要的通路时延可测试性及相应的单通路时延故障的分类 ,并介绍了三种精简通路集的通路时延测试
4)  Passage-testing
通路测试
5)  Instant /delayed recall
即时测试/延时测试
6)  path delay fault
通路时延故障
1.
Learning-based test generation for path delay fault of conditional sum adders;
学习策略实现的条件和加法器通路时延故障测试生成
2.
The problem of path delay fault test is addressed in this paper for parallel-prefix tree-like adders,which are kinds of high-speed adders.
时延故障对高速运算电路性能有着关键性的影响,本文对其中之一的并行前置树型加法器的通路时延故障测试作了研究。
3.
This paper gives a survey of the recent development of path delay testing,introduces the classification of single path delay faults according to testability,and analyses three approaches to reducing the number of paths to be tested during path delay testin
本文对目前通路时延测试领域的主要研究成果进行了综述 ,阐述了主要的通路时延可测试性及相应的单通路时延故障的分类 ,并介绍了三种精简通路集的通路时延测试
补充资料:怀卢延让(时延让新及第)
【诗文】:
冥搜忍饥冻,嗟尔不能休。几叹不得力,到头还白头。
姓名归紫府,妻子在沧洲。又是蝉声也,如今何处游。



【注释】:



【出处】:
全唐诗:卷834-22
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