1) The Design of Low Noise PLL Frequency Synthesizer
低相噪锁相源设计
2) low phase noise
低相噪
1.
In this scheme,the synthesizer contains a low-noise phase detector to achieve the performance of low phase noise and low spur level.
本方案采用了低底噪鉴相器,实现低相噪和低杂散指标。
2.
This article introduces a scheme which realized C-band low phase noise radar hopping frequency synthesizer,with PLL and mixer.
介绍了利用锁相环和混频技术,实现C波段低相噪跳频源的方案,该方案通过两个环路同时实现跳频及混频,步进36MHz,输出频率4428~5220MHz,具有低相位噪声,低杂散等特点。
3.
The design of a Ku-band frequency synthesizer with low phase noise and frequency agility is introduced which involves an integrative method to the local oscillator and excitation prompting.
介绍了一种Ku频段低相噪捷变频频率综合器设计方法。
3) Low phase noise
低相位噪声
1.
A low phase noise VCO(voltage controlled oscillator)for single chip UHF RFID Reader is proposed.
介绍了一种适用于UHF RFID(Radio Frequency Identification)阅读器的低相位噪声压控振荡器(VCO)电路。
2.
This article introduces an typical application of HMC440 which is an ultra low phase noise floor phase frequency detector produced by HITTITE.
介绍了HITTITE公司一款具有超低相位噪声基底的鉴频鉴相器HMC440在C波段锁相频率合成器中的应用。
3.
A novel method to develop a frequency synthesizer with wide frequency coverage, fast frequency switching speed, and low phase noise is proposed.
提出了一种宽相对覆盖、低相位噪声的捷变频频率合成方法。
4) Low-noise design
低噪声设计
1.
The main differences between low-noise design in machinery and noise control are compared herein.
比较了机器低噪声设计与噪声控制的主要区别,介绍了低噪声设计的一般特性和若干原理,提出了低噪声设计要结合于产品设计周期,同时又要兼顾到与设计周期的其它方面的高度交互作用。
5) low noise design
低噪声设计
1.
A modified low noise design method of CMOS charge sensitive preamplifier was proposed in this paper.
提出了一种改进的CMOS电荷灵敏前放低噪声设计方法,通过实例计算得到的噪声结果比现有方法都有不同程度的提高。
2.
This article analyze the signal processing circuit noise character of a radio proximity fuze, and investigate the low noise design based on the analysis result and the reflect wave from the target.
以某无线电近炸引信为例,分析了该引信的噪声特性,并根据噪声分析的结果以及该引信的回波信号的特征进行了低噪声设计研究,根据对低噪声设计分析的结果可以看出,本文所提出低噪声设计原则是有效的、可行的。
3.
Effective low noise design techniques guarantee to achieve 12.
高速高带宽的模拟调理电路的灵活设计,可以兼容多种IRFPA的信号读出电路;灵活配置的采样时钟控制,支持CDS和SHA两种采样模式,而且能够连续调节ADC的采样时钟相位;有效的低噪声设计措施,保证了系统能够真正实现12。
6) Design of Lock-in Amplifier
锁相放大器的设计
补充资料：噪噪切切
1.犹言嘈嘈切切。指弦乐器上大弦和小弦发出的高低不同的声音。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条