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1)  instruction parallel
指令并行
1.
Based on the in-depth research of FT-C55LP’s characteristics of instruction sets and instruction parallel, I have a comprehensive and detailed analysis of the instruction sets of FT-C55LP, and put forward a design plan of decoding controlling unit, which is divided into three modules: parallel instruction splitting, single instruction decoding, and decoded signal incorporating.
作者对FT-C55LP的指令集进行全面而详细的分析,在深入研究指令集特点和指令并行特征的基础上,给出了译码控制单元的设计方案。
2)  parallel instruction
并行指令
1.
The hierarchical memory management of BF535 is analyzed, and the memory in different region is described, According to the L1 and L2 RAM of the DSP, parallel instruction and FFT operation is evaluated.
其次,针对该DSP的L1、L2,进行了并行指令和FFT运算的性能评测。
3)  Instruction level parallelism
指令级并行
1.
In order to fully utilize the instruction level parallelism of the recent VLIW DSP processors, DSP programs have to be optimized by software pipelining.
为了充分利用VLIWDSP处理机的指令级并行性,必须使用软件流水技术对DSP程序进行优化。
2.
Instruction scheduling is used to exploit the instruction level parallelism(ILP)inherent in program through reordering its instructions.
指令调度通过调整指令之间的顺序来提高指令级并行度(ILP)。
3.
Improving the degree of the instruction level parallelism is not only an important trend for the development of the CPU architecture but also significant content of the course about "Computer Organization", "Computer Architecture".
提高指令级并行度是处理器体系结构发展的重要方向 ,也是当前计算机组织、计算机结构课程的重要内容之一。
4)  Inner ILP
指令内并行
5)  ILP
指令级并行
1.
ILP Based Multimedia Realtime Processing;
指令级并行的多媒体数据实时处理
2.
In order to exploit instruction level parallelism(ILP),multiple functional units with multi-ports register file are often used in very long instruction word(VLIW) processor.
分簇在不影响处理器ILP的前提下减少了每簇寄存器文件的端口数目,但对编译器提出了挑战,编译器必须将指令和操作数在簇间进行合理分配才能得到较好的指令级并行。
3.
This paper presents the architecture and implementation approach of multimedia data processing on the ILP(Instruction Level Parallelism)of DSP platform.
讨论了多媒体数据并行处理技术的结构和实现方法,并分析了DSP的指令级流水线结构、开发方法和实现技巧,同时在分析和重组数据流的基础上,给出了利用指令级并行流水线优化视频处理中DCT变换算法和运动搜索算法的实例。
6)  Instruction concurrency
指令并行性
补充资料:指令
指定计算机的操作和操作数或操作数地址的一组字符代码。由操作码和地址码组成。可被中央处理机理解和执行。操作码规定计算机操作的性质,地址码指出操作数所在地址和操作结果要送往的地址。参见“指令系统”。
说明:补充资料仅用于学习参考,请勿用于其它任何用途。
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