1) Clock gating cell
门控时钟单元
2) clock gating
时钟门控
1.
To lower the power dissipation of floating-point co-processor,the information of the decode stage in the integer unit pipeline was used to generate the micro-architecture clock gating signals so that the unused floating-point co-processor execution pipelines can be clock-gated.
设计中根据整点单元的译码级结果来产生针对浮点协处理器各数据路径的时钟门控信号,从而实现了微体系结构级的浮点协处理器时钟门控,在静态功耗基本不受影响的情况下,可以消除对应数据路径空闲状态的动态功耗。
3) clock-gating
门控时钟
1.
A low-power ternary D-type flip-flop design based on clock-gating technique;
基于门控时钟技术的低功耗三值D型触发器设计
2.
Low-power CMOS circuit design based on Clock-Gating;
基于门控时钟的CMOS电路低功耗设计
3.
The Design and Implementation of Low Power MCU Based on Clock-gating;
基于门控时钟的低功耗MCU的设计与实现
4) gated clock
门控时钟
1.
A zero-skew gated clock routing algorithm is proposed to solve this problem.
传统的时钟树布线算法可以扩展应用于门控时钟,例如在自底向上的合并过程中采用最小化合并电容方式。
2.
This flow could use the gated clock,the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.
这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
5) clock gating
门控时钟
1.
This paper analyses the disadvantages of many clock gating techniques and points out that they are obstacles in System-on-Chip(SoC) design.
门控时钟技术一直以来是降低芯片动态功耗的有效方法。
2.
In addition,zero bypassing,clock gating and truncation are used to reduce the switching activities and the power consumption.
为了降低功耗,设计基于行列分解的结构,采用了Loeffler的DCT/IDCT快速算法,并使用了零输入旁路、门控时钟、截断处理等技术,在满足设计需求的基础上降低了系统的功耗。
3.
In this paper, the methodology of clock gating is presented to decrease the power consumption.
本文在设计多点控制协议MPCP模块中,采用插入门控时钟这一技术以降低芯片功耗。
6) gating clock
门控时钟
1.
Application of automatic gating clock technology in SoC1000C
自动门控时钟技术在聚芯SoC1000C中的应用
补充资料：门控
门控
影像学术语。影像学检查(如CT、MRI、DSA)中，部分器官具有生理性运动，如心搏、呼吸，当成像时间长于这些器官运动的周期时即导致影像模糊。改良的方式之一即使用心电图和/或呼吸门电路控制采集信息的时相，如在心脏的收缩末期或舒张末期采集，从而获得的影像消除了移动伪影，结构显示清晰，且连续成像的影像处于同一时相，具有可比性。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条