3) high speed glide multiplier
高速流水定点乘法器
4) floating point multiplier
浮点乘法器
1.
Parameterized IP of floating point multiplier design method based on Verilog HDL is discussed in this paper,and three kinds of parameters are picked out.
为了对Verilog硬件描述语言(Hardware Description Language,HDL)的浮点乘法器知识产权(Intellectual Property,IP)核参数化设计方法进行详细描述,以一种浮点乘法器的参数化设计为例,介绍了其可重配置的三种功能参数,提出了尾数乘法运算采用基4Booth编码器对部分积压缩,然后采用一种将阵列与树混合的结构,对部分积划分成几个子块并行运算,最后结果用超前进位加法器累加输出。
2.
Using Verilog HDL,a design of 32 b single precision floating point multiplier based on FPGA is presented.
采用V erilog HDL语言,在FPGA上实现了32位单精度浮点乘法器的设计,通过采用改进型Booth算法和W a llace树结构,提高了乘法器的速度。
5) floating-point multiplier
浮点乘法器
1.
Research on 32 Bit High-Speed Floating-Point Multiplier Design;
32位高速浮点乘法器设计技术研究
2.
A high-speed floating-point multiplier is presented in this paper.
文章介绍一种32位浮点乘法器软IP的设计,其部分积缩减部分采用修正Booth算法,部分积加法采用4-2压缩树结构,最终carry、sum形式部分积采用进位选择加法器完成,乘法器可以进行32位浮点数或24位定点数的乘法运算。
3.
Multiple-input floating-point multiplier is usually composed of several double-input floating-point multipliers,and it s inevitable to increase logic resource and processing latency,which makes it harder and harder to meet the requirement of high-speed digital signal processing.
传统的多输入浮点乘法运算是通过级联二输入浮点乘法器来实现的,这种结构不可避免地使运算时延和所需逻辑资源成倍增加,从而难以满足高速数字信号处理的需求。
6) fixed-point scalar multiplication
定点标量乘法
补充资料：定点
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参考词条