Incremental redundancy Hybrid ARQ schemes based on parallel concatenated LDPC codes and its performance analysis

Performance Analysis of LDPC Decoding Algorithm;

Study and Development of LDPC Coding;

Analysis of LDPC Decoding Algorithm Based on Serial Schedule;

Iterative phase synchronization algorithm based on modified Costas loop for LDPC coded systems;

Algorithm of flipping-bit decoding for LDPC code;

Applied quasi-cyclic LDPC codes from doubly-extended RS code and cyclic MDS code;

Improved decoding algorithm for irregular low-density parity-check codes and its implementation with DSP;

Study on Some Key Problems of Low-Density Parity-Check Codes;

The invention and development of low-density parity-check codes (LDPC) narrow the gap between real system performance and channel capacity.

Study on LDPC codes based on cyclic-shift identity matrix;

Extended LDPC codes based on linear row decomposition;

Configurable min-sum decoding algorithm for LDPC codes;