1) multi-asynchronous clock design
多时钟域设计
3) multi-clock domain
多时钟域
1.
The paper analyses the metastability which is caused by communicating data between multi-clock domain and effect of metastability to the circuit.
分析了多时钟域数据传递设计中亚稳态的产生以及对整个电路性能和功能的影响,以一款异步并行通信接口芯片的设计为例,详细描述了采用同步器、FIFO实现8位并行数据到16位并行数据的两时钟域异步转换的过程。
2.
An important problem in multi-clock domain design is how to avoid metastability.
多时钟域设计的一个难题是如何避免亚稳态的产生。
4) clock design
时钟设计
1.
PECL signal makes this logic suitable for high-speed ADC clock design.
PECL(正电压射极耦合逻辑)信号作为一种适合高速逻辑互联的电平标准,越来越多地应用在高速A/D转换器的时钟设计中。
2.
This article discusses five different clock design schemes in FPGA design,analyzes the advantages and disadvantages of these different schemes as well as some critical points in their design.
探讨了FPGA设计过程中5个不同的时钟设计方案,对这些不同方案的优点、缺点和在设计中需要注意的问题进行了分析,并提出了一些合理建议。
3.
Six clock design measures for the field programmable gate array(FPGA) are described in this paper which preset a credible clock design according to the setup time,hold time and synchronous principle.
对于现场可编程门阵列(FPGA)常见的6种时钟设计,根据建立时间和保持时间的要求,按照同步设计原则,分别给出可靠的时钟设计方案。
5) multi-clock SOC
多时钟域SOC
1.
This paper presents the TAM optimization and test scheduling algorithm for multi-clock SOC,and it aims at decreasing test time of multi-clock SOC.
该文提出了用于多时钟域SOC的TAM优化与测试调度算法,以减少多时钟域SOC的测试时间。
6) one clock design
单时钟设计
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