1.
Research and Implementation of a DLL Based High Frequency Clock Generator;
基于DLL的高频时钟产生电路的研究与实现
2.
Two Phase Non-Overlap Clock Generator with Independent Pulse Width Adjusting
一种独立调节两相脉宽的不交叠时钟产生电路
3.
Design of Clock Generation and Drive Circuits in High Speed CIS System
高速CIS时钟发生电路及驱动电路设计
4.
The sampling clock generator must also have adequate spectral purity.
时钟发生电路固有的抖动应该足够小。
5.
A Clock Generation Circuit for High-Resolution ∑Δ Modulator;
适用于高精度Δ调制器的低电压时钟发生电路
6.
A Novel High-precision Multi-phase Clock-generator Circuit;
一种新颖的高精度多相时钟发生电路设计
7.
Circuit design of spread-spectrum clock generator based on DP standard
基于DP标准发射端扩频时钟发生器电路设计
8.
Trigger circuit, power supply circuit, clocking circuit and reset circuit are the main circuits on the main board.
触发电路、供电电路、时钟电路、复位电路是主板上最主要的电路。
9.
boosted-high level clock generator
升压高电平时钟发生器
10.
TV station clock mark generator
电视台时钟台标发生器
11.
a unit of inductance in which an induced electromotive force of one volt is produced when the current is varied at the rate of one ampere per second.
电感单位当电路中的电流强度在一秒钟内的变化为一安培产生的电动势为一伏特时电感为一亨利。
12.
Generation of Multi-Wavelength Optical Pulses and Electrical Clock Signal Utilizing Optoelectronic Oscillator with Single Light Source
利用单光源光电振荡器实现多波长光脉冲与电时钟信号产生
13.
Property Generation Method for Model Checking on Clock Domain Crossing Design
面向模型检验的跨时钟域设计电路特性生成方法
14.
The Data and Clock lines are both open collector.
数据和时钟线都是集电极开路的。
15.
Analysis of the Clock Skew in ASIC Design
专用集成电路设计中的时钟偏移分析
16.
The Design of 1GHz Clock Circuit with FPGA;
基于FPGA的1GHz时钟电路设计
17.
Design of 2.5GHz Full Speed Clock and Data Recovery Circuit
2.5GHz全速率时钟数据恢复电路的设计
18.
Research and Design of High Speed Clock Recovery Circuit on ASIC
高速时钟恢复电路的ASIC研究与设计