1.
Realization of LL-DPL in FPGA/CPLD
超前滞后型数字锁相环LL-DPLL在FPGA/CPLD中的实现
2.
phase lead-lag network
相位超前-滞后电路
3.
A Novel All-digital Phase-locked Loop Z-domain Model in Time Domain
一种新型的时间域全数字锁相环Z域模型
4.
A New Low Power All-Digital PLL Design Based on VHDL
基于VHDL的一种低功耗新型全数字锁相环设计
5.
Design and Implementation of An Improved Digital Phase Locked Loop Based on VHDL
基于VHDL的一种改进型数字锁相环的设计与实现
6.
Design and Realization of the High Speed ADPLL Based on the 65nm Process
基于65nm工艺的超高速全数字锁相环的设计和实现
7.
Research and Design of All-digital PLL with High Frequency and Low Jitter Performance;
高速低抖动全数字锁相环的设计研究
8.
The Design of Digital Circuits in CMOS Charge-Pump Phase-Locked Loop;
CMOS电荷泵锁相环中的数字电路设计
9.
APPLICATION OF ISPLSI1016 IN DIGITAL PHASE-LOCKED LOOP;
ispLSI1016在数字锁相环中的应用
10.
Detetion of Harmonic Waves Based on DPLL Synchronous Sampling
基于数字锁相环同步采样的谐波检测
11.
Design of Digital Phase Locked Loop Used in SDH Equipment Clock
SDH设备时钟中的数字锁相环设计
12.
The Implementation and Analysis of Digital Phase-locked Loop Based on FPGA
基于FPGA的数字锁相环实现与性能分析
13.
Design of all digital phase locked loop based on FPGA
基于FPGA的全数字锁相环的设计
14.
Improvement and Application of Digital Costas Phase-locked Loop
数字Costas锁相环的改进及应用
15.
Research on Adpll-Basedtime Digital Converter
基于全数字锁相环的时间数字转换器的研究
16.
The Design of the Lead-Lag Compensator for Boiler Steam Temperature Feedforward Control
锅炉汽温超前—滞后补偿型前馈控制器设计
17.
Non-linear Analysis of Second-order Phase-locked Loop by Phase Plain Approach in Numeric Domain
二阶锁相环路的数字域相图法非线性分析
18.
Study on Key Techniques of Digital Up/Down Conversion and Digital Phase-Lock-Loop;
数字上下变频及全数锁相环关键技术研究