1.
Design of a 3-stage Pipelined Modular Multiplication and Addition Unit for ECC
![点击朗读](/dictall/images/read.gif)
一种适合ECC的三级流水模乘加单元设计
2.
In other words, F respects addition, multiplication and identity element.
![点击朗读](/dictall/images/read.gif)
换言之,F保持加,乘法和单位元。
3.
FPGA Design of Multiply-accumulate Module in Image Compression Algorithm Based on BP Neural Network
BP神经网络图像压缩算法乘累加单元的FPGA设计
4.
Design and Implementation of the Asynchronous Sub-Word Parallel MAC Unit
![点击朗读](/dictall/images/read.gif)
异步子字并行乘累加单元的设计与实现
5.
Addition, subtraction, multiplication, and division are binary operations.
![点击朗读](/dictall/images/read.gif)
加、减、乘、除都是二元运算。
6.
Click the cells in your document that contain the numbers you want to multiply.
![点击朗读](/dictall/images/read.gif)
单击文档中含有要乘以的数字的单元格。
7.
Optimal solution on weighted total least absolute deviations
![点击朗读](/dictall/images/read.gif)
关于多元加权全最小一乘法的最优解
8.
The Preliminary Discussion of the Passenger Car Bussiness Unit of Dongfeng Motor Corporation;
东风汽车公司乘用车业务单元国际化战略初探
9.
RLS Algorithm on Array Antenna with Failure Cells;
![点击朗读](/dictall/images/read.gif)
阵列天线单元失效的递推最小二乘算法应用
10.
multielement prestressing
![点击朗读](/dictall/images/read.gif)
多单元构件预加应力
11.
terminal heating & cooling units
![点击朗读](/dictall/images/read.gif)
终端加热和冷却单元
12.
vertical turner flexible machine cell
![点击朗读](/dictall/images/read.gif)
立式车削柔性加工单元
13.
Condition of Rank Preservation or Adding a Group Elements to the Interval Logarithm Least Square Method;
区间数对数最小二乘法增加元素的保序性条件
14.
Simple Weighted Least Squares on Dealing with Heteroscedasticity and its SAS Programme
![点击朗读](/dictall/images/read.gif)
一元加权最小二乘估计处理异方差性及SAS实现
15.
Class allows for simple fraction arithmetic -- addition, subtraction, multiplication, and division.
这些可以完成简单的分形算术--加、减、乘、除。
16.
A permanent change could not be made to the cell. The selected cell is probably protected.
单元格不能保存永久变化.可能单元格已加保护.
17.
CaD = Canadian dollar
![点击朗读](/dictall/images/read.gif)
加元 (加拿大货币基本单位)
18.
The Design and Realization of Multiplier in 64-bit High Performance Embedded CPU;
![点击朗读](/dictall/images/read.gif)
64位高性能嵌入式CPU中乘法器单元的设计与实现