1.
Design of FFT IP Core and Research of Design for Test
![点击朗读](/dictall/images/read.gif)
FFT IP核设计及其可测性设计的研究
2.
Testable Design and Testing for the OR-Coincidence Logic System;
![点击朗读](/dictall/images/read.gif)
或—符合逻辑系统的可测性设计与测试
3.
The DFT and Test Generation of Garfield;
![点击朗读](/dictall/images/read.gif)
Garfield芯片的可测性设计及测试生成
4.
The Research on SoC Test and Design for Testability;
![点击朗读](/dictall/images/read.gif)
系统级芯片的测试与可测性设计研究
5.
Design-for-Testability and Test of Garfield Series SoC’s
![点击朗读](/dictall/images/read.gif)
Garfield系列SoC芯片可测性设计与测试
6.
Executing Module Design and DFT of 32-bit RISC CPU;
![点击朗读](/dictall/images/read.gif)
32位RISC CPU运算模块的设计及可测性设计
7.
The Research on Design for Testability of FPGAs;
![点击朗读](/dictall/images/read.gif)
基于FPGA的可测性设计方法研究
8.
The Design for Testability and the Circuit of DSPC50;
![点击朗读](/dictall/images/read.gif)
DSPC50的可测性设计及电路实现
9.
Testability Design for SoC Based on IDDQ Scanning
![点击朗读](/dictall/images/read.gif)
基于IDDQ扫描的SOC可测性设计
10.
Design for Testability of Memory in GPS Baseband Chip
![点击朗读](/dictall/images/read.gif)
GPS基带芯片中存储器的可测性设计
11.
Design for Testability and Implement Technology in ASIC Design
![点击朗读](/dictall/images/read.gif)
ASIC集成电路的可测性设计与技术实现
12.
Optimal Testability Design of Circuit Boards Based on JTAG
![点击朗读](/dictall/images/read.gif)
基于JTAG的电路板可测性设计分析技术
13.
The Researches on Mixed-Signal Test and Design for Testability;
![点击朗读](/dictall/images/read.gif)
数模混合信号芯片的测试与可测性设计研究
14.
Research on Circuit Fault Diagnosis and Low-Power Test;
![点击朗读](/dictall/images/read.gif)
电路故障诊断可测性设计及低功耗测试研究
15.
VLSI Auto Testing and Design for Test;
![点击朗读](/dictall/images/read.gif)
集成电路自动测试方法及可测性设计研究
16.
Research on Design for Testability and Test Algorithm of Embedded Memory
![点击朗读](/dictall/images/read.gif)
嵌入式存储器的可测性设计及测试算法研究
17.
Structural design-for-testability of accumulation-based testing for DSP data path
![点击朗读](/dictall/images/read.gif)
DSP数据通路基于累加器测试的结构可测性设计
18.
Design Validation and Usability Testing
![点击朗读](/dictall/images/read.gif)
设计验证和可用性测试