1) quiescent power dissipation current
静态功耗电流
1.
The other important conclusion of this paper is that we prove quiescent power dissipation current must be a main factor while evaluating the effect of shielded packages using CMOS device.
通过分析,指出了当前屏蔽材料封装存在的不足,以及在采用CMOS器件考察抗辐射屏蔽封装材料时应该重点考虑静态功耗电流。
2) Super-low quiescent powerdissipation current
超低静态功耗电流
3) standby power
静态功耗
1.
The paper analyses the standby power dissipation of standard SRAM 6-T cells.
为了解决存储单元的亚阈值泄漏电流问题,分析了在深亚微米下静态随机存储器(SRAM)6-T存储单元静态功耗产生的原因,提出了一种可以有效减小SRAM静态功耗浮动电源线的结构,并分析在此结构下最小与最优的单元数据保持电压;最后设计出SRAM的一款适用于此结构的高速低功耗灵敏放大器电路。
2.
As technology evolves, the threshold voltage will be re- duced accordingly, which results in an exponential increase of standby power.
随着工艺的发展,器件阈值电压的降低,导致静态功耗呈指数形式增长。
4) static power
静态功耗
1.
The static power exceed the dynamic power in microprocessors as the feature size shrinks,especially for on-chip L2 caches.
随着集成电路制造工艺进入超深亚微米阶段,静态功耗在微处理器总功耗中所占的比例越来越大,尤其是片上二级Cache。
2.
Simulation results prove that active power of proposed Zipper CMOS full-adder can be reduced by up to 37%,5% and 7%,and static power can be reduced by up to 41%,20% and 43% as compared to the standard,the dual threshold voltage,and the multiple supply Zipper CMOS domino full-adder under similar delay time,respectively.
仿真结果表明,在相同的时间延迟下,与标准Zipper CMOS多米诺全加器、双阈值Zipper CMOS多米诺全加器、多电源电压Zipper CMOS多米诺全加器相比,新型Zipper CMOS多米诺全加器动态功耗分别减小了37%、35%和7%,静态功耗分别减小了41%,20%和43%。
5) dynamic consumption current
动态功耗电流
1.
Experiments also suggest that research on the TDEs of SRAM and ROM should take the static consumption current and dynamic consumption current as the effective criterions for the damage threshold of TDEs other than testing the data access function only,because the static consumption current and dynamic consumption current are all sensitive to TDEs.
实验还表明,研究SRAM、ROM的总剂量辐射效应,只对数据存取功能进行测试是不完善的,器件的静态功耗电流与动态功耗电流也是总剂量辐射效应的敏感参数,应该作为总剂量辐射效应失效阈值的有效判据。
6) low leakage power
低静态功耗
1.
Compared with the current cache architecture for low power, this architecture with resizable ways and low leakage power has the characteristic of fewer additional logics, simpler .
该结构通过门控Gnd技术来动态地关闭或开启部分cache路,使得cache结构可以在低功耗配置和正常配置之间切换,从而达到降低静态功耗的目的。
补充资料：标准冲击电流波形(见冲击电流发生器)
标准冲击电流波形(见冲击电流发生器)
standard impulse current wave form
blaozhun ehonglld}0n4一u box]ng标准冲击电流波形(standard impulse currentwave form)见冲击电流发生器。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条